Networking Hardware¶
Last updated: 2026-04-11
Recent Finds¶
NVIDIA Spectrum-X Photonics: Co-Packaged Optics Switches for Million-GPU AI Factories (H2 2026)¶
NVIDIA's Spectrum-X Photonics marks the first major commercial deployment of co-packaged optics (CPO) in a switch ASIC from a dominant vendor. Key specs: 100 Tb/s (128×800G or 512×200G) and 400 Tb/s configurations, with optical engines integrated directly on-die — eliminating electrical traces between ASIC and optical transceiver. Claimed benefits: 3.5× power efficiency, 10× resiliency, 4× fewer lasers vs. pluggable optics, 1.3× faster deployment. Available H2 2026. The silicon photonics ecosystem (TSMC, Coherent, Lumentum) is now productized around NVIDIA's demand signal. Broader implication: CPO will become the de-facto interconnect standard for 51.2T+ AI switches. IDTechEx projects the CPO market to grow at 37% CAGR, reaching $20B by 2036.
Broadcom Tomahawk 5-Bailly: 50,000+ CPO Switches Shipped; Tomahawk 6 "Davisson" at 200G/lane Previewed (Apr 2026)¶
As of early April 2026, Broadcom has shipped over 50,000 Tomahawk 5-Bailly CPO switches — establishing CPO as commercially deployed at hyperscale, not merely sampled. Tomahawk 5 specs: 100G/lane optics, 30%+ system-level power savings vs. pluggable modules. The third-gen Tomahawk 6 "Davisson" is previewed as the industry's first 102.4 Tbps switch with 200G/lane optical interfaces integrated via TSMC's COUPE packaging. Simultaneously, Marvell's "Photonic Fabric" is being re-rated by analysts as an optical networking positioning play for 1.6T interconnects. Market implication: the pluggable transceiver era for top-of-rack AI cluster switches is over — CPO is the shipping baseline. The competitive battleground has shifted to 200G/lane gen-3 platforms and packaging yield. Together with NVIDIA Spectrum-X Photonics (400 Tb/s, H2 2026), this confirms that both major switch ASIC vendors have fully committed to CPO.
Co-Packaged Optics in 2026: From Demo to Commercial (EDN)¶
State-of-the-market analysis confirming CPO has reached an inflection point: two of the largest switch ASIC vendors are now shipping or sampling first-generation CPO products (NVIDIA and Broadcom both announced). The transition from pluggable (QSFP-DD, OSFP) to co-packaged resolves the "last inch" power problem — electrical traces from cage to ASIC consume significant power and limit bandwidth density at 51.2T+. Technical challenges: laser reliability (MTBF requirements vs. CPO accessibility for repairs), thermal management of integrated photonics, and standardization (OIF CPO specification still evolving). Key tradeoff: CPO is not field-replaceable — a dead laser may mean replacing the entire switch linecard.
Cisco Silicon One G300 — Next-Gen ASIC at Cisco Live EMEA 2026¶
Cisco unveiled the Silicon One G300 ASIC supporting up to 102.4 Tb/s switching capacity with programmable pipeline support. Significant market signal: programmable networking silicon grew from <3% market share in 2020 to over 18% by 2026 — fixed-function ASICs are being displaced. The G300 targets both core routing (replacing ASR 9000-era linecards) and high-density data center switching, with a unified architecture reducing the traditional router/switch product divide.
P4 + DPDK on SmartNICs: Performance Benchmarking (iWave Global)¶
Technical deep-dive into combining P4 programmable pipelines with DPDK at the SmartNIC layer. Key result: equivalent packet processing functionality in ~5,000 lines of P4 vs. millions of lines of C with DPDK alone — dramatic reduction in implementation complexity. The hybrid approach (P4 for match-action pipeline, DPDK for exception path and control plane) is becoming the architecture of choice for building software-defined data center switches without firmware update cycles.
Montage Technology PCIe 6.x / CXL 3.x Active Electrical Cable Solution (January 2026)¶
Montage's AEC announcement for PCIe 6.x/CXL 3.x interconnects addresses the emerging need for coherent memory pooling in disaggregated AI infrastructure. PCIe 8.0 standardization (256 GT/s per lane, ~1 TB/s bidirectional on x16) is in progress. Marvell's $540M acquisition of XConn signals aggressive investment in CXL switching silicon — enabling many-to-many memory sharing across compute nodes in a rack. CXL.mem is becoming the key protocol for GPU/accelerator memory expansion.
Core Concepts¶
ASIC Design Landscape¶
- Fixed-function ASICs (Broadcom Tomahawk, Trident): Hard-coded forwarding pipelines. Highest performance, lowest power, no flexibility. Dominated the market for 20 years.
- Programmable ASICs / NPUs: Cisco Silicon One, Intel Tofino (P4-programmable), Barefoot Networks heritage. Software-defined forwarding — update behavior without new silicon.
- SmartNICs / DPUs: Nvidia BlueField, Marvell Octeon, Broadcom Stingray. Move host networking, storage, and security offload off the CPU. Running full Linux stacks on-NIC.
- Trend: Line between switch ASIC and SmartNIC is blurring as DPUs gain switching capabilities.
P4 — Programming Protocol-Independent Packet Processors¶
- Match-Action Tables (MAT): Core abstraction. Match packet header fields → execute action (forward, drop, modify, meter, encap).
- Reconfigurable Match Tables (RMT): Physical representation in programmable ASICs — configurable width, depth, and match type.
- P4Runtime API: Standard gRPC-based control plane for populating MAT entries at runtime.
- Use cases: Custom routing protocols, telemetry (INT — In-band Network Telemetry), stateful firewalls, load balancing, SRv6, QUIC offload.
DPDK — Data Plane Development Kit¶
- Kernel bypass framework for user-space packet processing at line rate.
- Poll Mode Drivers (PMD) eliminate interrupt overhead — CPU spins polling the NIC ring buffer.
- Memory: Huge pages (2MB/1GB), NUMA-aware DPDK mempool.
- Typical throughput: 10-100 Mpps per core depending on packet size and processing complexity.
- Works with physical NICs (Intel IXGBE, Mellanox MLX5) and virtual (virtio, VHOST).
PCIe & CXL Interconnects¶
| Gen | Raw Rate (per lane) | x16 bandwidth | Key Use |
|---|---|---|---|
| PCIe 4.0 | 16 GT/s | ~32 GB/s | Current GPUs |
| PCIe 5.0 | 32 GT/s | ~64 GB/s | Latest CPUs/GPUs |
| PCIe 6.0 | 64 GT/s (PAM4) | ~128 GB/s | Emerging AI accelerators |
| PCIe 7.0 | 128 GT/s | ~256 GB/s | In development |
- CXL (Compute Express Link): Built on PCIe PHY. Three sub-protocols:
- CXL.io: PCIe-compatible I/O (devices, config space)
- CXL.cache: CPU-device cache coherency
- CXL.mem: CPU accesses device memory with host-managed coherency
- CXL 3.x: Multi-level switching (CXL fabric), peer-to-peer device-to-device coherency, memory pooling across rack.
Optical Networking¶
- 400G/800G ZR/ZR+ coherent: High-capacity DWDM transceivers moving into pluggable (QSFP-DD) form factors. Eliminating dedicated transponder shelves.
- Co-packaged optics (CPO): Optical dies co-packaged with switch ASIC to reduce electrical trace length and power. Intel, Broadcom, and Cisco pursuing this for 51.2T+ switches.
- Silicon Photonics: CMOS-compatible optical components enabling mass production. Key vendors: Intel, Cisco (Acacia), II-VI/Coherent.
SmartNIC / DPU Vendors¶
| Vendor | Product | Notes |
|---|---|---|
| Nvidia | BlueField-3 | Arm Cortex A72 + ConnectX-7. Dominant in AI/cloud |
| Marvell | Octeon 10 | MIPS + Arm, strong in telco/enterprise |
| Broadcom | Stingray | Arm-based, integrated PCIe switch |
| AMD/Pensando | Elba | Strong storage offload, acquired by AMD |
| Intel | IPU (Mount Evans) | Custom Arm cores, OCP contribution |
Open Questions¶
- Will P4 become the universal data plane programming model, or will vendor-specific DSLs persist due to hardware-specific optimizations?
- How does CXL memory pooling change the economics of AI training clusters — can shared CXL memory replace HBM for some workloads?
- CPO is not field-replaceable — how will hyperscalers manage laser failure in deployed CPO switches? Will they maintain optical-module spares at the linecard level?
- Will the OIF CPO standard converge before 2027, or will NVIDIA/Broadcom ship incompatible proprietary CPO form factors?
- How do SmartNICs/DPUs change the threat model — running full Linux on the NIC means a new attack surface adjacent to the hypervisor.